Thin-film transistor liquid-crystal display (TFT-LCD) panels are known in the art. As shown in FIG. 1, a typical TFT-LCD display panel 10 comprises a display module 20 having a plurality of pixels 21 arranged in a two-dimensional array. These pixels are controlled by a plurality of data lines D1, D2, . . . , Dn and a plurality of gate lines G1, G2, . . . , Gm. The data lines are connected to a data source driver 30 and the gate lines are connected to a gate-line driver 40. A printed circuit board (PCB) 50 containing circuits necessary to convert image data into voltage signals is connected to drivers 30 and 40 via a control bus 52.
In recent years, amorphous silicon gate drivers (ASGDs), which are integrated circuits (ICs) directly fabricated on the same substrate that supports the pixel array, are replacing silicon-chip gate driver ICs for gate-line driving of the LCD display. The ASGD technology allows for fewer external components, thus reducing the cost of manufacturing.
As shown in FIG. 2(a), an exemplary ASGD gate-line driving circuit contains a shift register module 70 that has a plurality of shift registers. Each shift register (SR) has an input terminal (In), an output terminal (Out), a voltage source terminal (Vs), a first clock signal terminal (Ck1) and a second clock signal terminal (Ck2). Signals coming from the control bus 52 (see FIG. 1) for gate-line driving include a negative voltage Vss, a start pulse signal Vst, a clock signal Vck and an inverted clock signal xVck. The inverted clock signal xVck has a phase 180° behind the phase of the clock signal Vck. Vss is applied to the voltage source terminal (Vs) of every SR. Vst is applied to the input terminal of the first SR in the SR module. Vck and xVck are applied to clock terminals Ck1 and Ck2, respectively, of each SR in an alternate fashion so that every odd-numbered SR is connected as Vck→Ck1 and xVck→Ck2, and every even-numbered SR is connected as Vck→Ck2 and xVck→Ck1. The output terminal of a SR connects to a gate line of the LCD array. Each gateline connects to one row of pixels.
The SRs in the shift register module 70 are connected in a cascade manner. When a pulse Vst indicating the beginning of a frame arrives at the first shift register SR001, SR001 provides an output pulse to the first gate line, Gateline001, in response to a clock signal Vck. The same output pulse is also provided to the input terminal of the second shift register SR002. In response to the inverted clock signal xVck, the second shift register SR002 provides an output pulse to the second gate line, Gateline002. The output pulse from SR002 is also provided to the input terminal of the third shift register SR003 so that an output pulse from SR003 is provided to the third gate-line, Gateline003, in response to the clock signal Vck. In this manner, every gate line receives a positive voltage pulse in sequence. The odd-numbered SRs are operated in synchronization with the clock signal Vck, whereas the even-numbered SRs are operated in synchronization with the inverted clock signal xVck. A time sequence of Vck, xVck, Vst and SR outputs is shown in FIG. 2(b).
Since SRs are connected in a cascade manner, one defective or failed SR would effectively disable all of the subsequent SRs in the shift register module 70. For that reason, a defective SR must be replaced whenever it occurs. However, since the gate driver is fabricated on the same substrate that supports the display pixel array, replacing one SR would mean discarding the entire display panel altogether. This is very cost ineffective.
Thus, it is advantageous and desirable to provide a method and device for repairing the shift register module while other components of the display panel are preserved.